In digital CMOS circuits, power dissipation is proportional to clock frequency. If the clock frequency is reduced to reduce the power dissipation, the data throughput of the circuit is also reduced, unless data is processed in parallel by additional data processing channels. If, for example, the clock frequency is halved, the original throughput can be maintained if two consecutive data samples are processed in parallel. As long as the additional processing channel does not double the overall circuitry, overall power dissipation will be reduced, or a higher data throughput can be achieved for the same power dissipation.
Hard disk drive technology is one area where reduction of power dissipation is important. The read decoding circuitry of such hard drives operates at a very high frequency and is typically implemented with digital CMOS circuits. Reduction of the clock frequency of hard drive read decoding circuitry would provide a significant reduction in power dissipation.